basic logic gates lab report discussion
In order for an OR Gate to make the circuit work, it at least needs one of the inputs to have a 1 value hence will explore FPGA resources utilized to develop logic in hardware. 
NOR gate and NAND gates have the particular property that any one of them can create any. It should be noted that the transition period for the rising and falling edges of the same gate may not necessarily be the same, although it is normally desirable to have a symmetrical transition. The NAND and NOR gates are universal gates. The signals passing through a gate take a certain amount of time to propagate from its inputs to the output. TTL and ECL are based upon bipolar transistors. Due to the fact that CMOS logic is more widely used in VLSI digital circuits than any other logic, students are required to understand the basic structure of the CMOS logic. Course Hero is not sponsored or endorsed by any college or university. CMOS logic consumes far less power than MOS or bipolar logic. 0
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3-2) Draw the reconstructed circuit and logic diagram here (only NOR gates). 231 0 obj
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You will need to build a program that provides retirement estimates based on user inputs. xb```b``][ |,@Q Figure 5-1 An inverter operation generated by the use of NAND gate, Figure 5-2 An AND operation generated by the use of two NAND gates, Figure 5-3 An OR operation generated by the use of three NAND gates. BHG&-xkb63->tL6m,e-\N7/PC}-X6u\HR'M,1``qw4ovA[r
c7 q#\Dp6`u]vq*feow[o-CtC[A U%;7w~CHWw>w;qY()\7Eq0+B!^ ZXu^8Q?~|'p&?r%gL(ox`:/YKKs_(!Ha)k AND, NAND, OR, and NOR representing DeMorgans theorems can be obtained. Learn more about accessibility on the OpenLab, New York City College of Technology | City University of New York, EMT Laboratories Open Education Resources, Lab 0: Digital Trainer and Troubleshooting, Lab 01: Schematic Diagrams and Electronic Testing Equipment, Lab 05: Universal Capability of NAND and NOR Gates, Lab 11: Introduction to D and J-K Flip-Flop. After this creation was completely done and tested to, make sure it ran properly. Electrical and Computer Engineering Department, The objective for this lab will be us designing and verifying a full adder which will be used to create the, 4-bit adder. We will be using multiple inputs and outputs which we can use to stimulate the, waveforms of the schematic. TTL has a well-established popularity among logic families. 3 shows a CMOS inverter circuit. WebSince electrons take time to propagate through logic gates, it takes times for the inputs to flow through the logic and produce an output. 0000003695 00000 n
Logic gates function as the basic cells of digital electronics and serve as the core elements of all modern computers. h word/document.xml}n}B662h,^;!q88Iek98zs9`I$r3VDQH'eRccGlw(?mM6cR5P/L\xon}u ,?s|GT]7T@OO9e9*}X_Ig=-q
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B?&Fc This circuit adds together, three 1-bit values and produces a 2-bit binary output where the least-significant bit is called si (or just S), and the most-significant bit is called ci+1 (or Cout). A truth table is a table showing all possible values at the inputs of a digital circuit and the corresponding value of the output. 0000000016 00000 n
How many inverters could be formed using a 7400 NAND IC. z, /|f\Z?6!Y_o]A PK ! In practice, this is advantageous since 0000019247 00000 n
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Here you will see the three different inputs and two different outputs. 
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Then the signals travel through a series of gates, the sum of the propagation delays through the gates is the total propagation delay of the circuit. Why would a designer want to form an AND gate from two NAND gates? So we went ahead and created two 2 of the input XOR gates. xref
3) Then reconstruct the circuit above using only NOR gates. Generally speaking, the starting point of the transition process depends upon the threshold point of the gate in question, and the finishing point of the transition process depends upon the threshold point of the following gate. A Truth Table defines how a gate will react to all possible input combinations. 0000011065 00000 n
AD$ V*"Rb)'D+M8$N3a Q0xI>pMC`,XH'EI4.u6#vR,[,[y9n|]6'! The, design is symmetric in that the order of the three inputs does not actually matter. All seven basic logic gates have different rules for their truth table. 
2-input AND gate b. ?pn\}(n~~jA;8@'gNpB[hq\^(E=o}^ {*. 0000000016 00000 n
However, this is not a required step for this lab. This will be very, similar to the function we did in lab 1 and lab 2. Webnot sufficient to implement complex digital logic functions. 2) Complete the Truth table (Table 5-1) and measure the voltages of V 0000001745 00000 n
Conclusion / Summary: Realization of Experiment (3) Conducting Experiment (3) Team Work (3) Data Collection (3) Data Analysis (3) Computer Use (3) Discipline and Precautions (2) Total Marks (20) Obtained Marks Implement the basic logic gates using universal gates WebBasic Logic Gates X Objectives: The objectives of this experiment are to: 1. Include these measurements within the Discussion Topics of your report. 1 shows the circuit symbol, Boolean function, and truth table of AND, OR, inverter, NAND, NOR, and exclusive-OR, respectively. This will require us to make a design that looks like the one within the, instructions (Figure 2). Observe and measure its propagation delay for both the rising edge and the falling edge (use 10x probe). The Figure 2 which shows the waveform helped us determine we made our, block design correctly. Understand gate level minimization. Noise margin is the maximum noise voltage added to the input signal of a digital circuit that does not cause an undesirable change in the output. Suppose logic 0 is 0V and logic 1 is 5V, ideally. As those We see some defects as the logic is settling, like tiny spikes, but it eventually settles to the same value as your behavioral simulation. An OR Gate works in the opposite way of an AND Gate. Invalid logic voltage levels light neither indicator. 0000012195 00000 n
Now that you are able to use the NAND and inverter, use them to construct an AND gate. Exceeding the specified maximum fan-out (or load) may cause a malfunction because the circuit cannot supply the power demanded from it. 0 1 1 0 0 0 For instance, the standard TTL gate will typically have a maximum fan-out of at least 10. Connect one of the inverters as shown in Fig. Input B 0 1 0 1. 2. Fig. To We will be expanding on our knowledge and making more complicated, functions. a. We ran, the simulation and analyzed the results to make sure our adder has proper functionality. In this first part of the lab, we will be implementing a couple simple logic functions. N _rels/.rels ( j0@QN/c[ILj]aGzsFu]U
^[x 1xpf#I)Y*Di")c$qU~31jH[{=E~ Power dissipation is the supplied power required to operate the desired logic function. 0000008952 00000 n
They are widely used in large scale integrated circuits because of their high component density and relatively low power consumption. Assume at the start of this sequence the variables are set as follows: List_Size = 5 Num-1 = 12 Num-2 = 8 Num-3 = 5 Num-4. Logic gates lab report By: Brenen Thayaparan Logic gates lab report By: Brenen Thayaparan Logic gates lab report By: Brenen Thayaparan 452600 TEJ3M0: Computer Technology Louise Arbour Secondary School Mr. Lowe To study the truth tables of various basic logic gates using Logisim 2. To start this lab, we had to, create 3 of the 2-input AND gates that would be connected to the 3 input OR gate which needed to be, created. B|,f>~pF20]oC `5o`"n`rtl R"[/X6d6d/ZFG&{A#e]G&yl+:e*Q(DJY *pNzPP=080:pvYgav E}Xs~9]m s~IkTlFD>+cb_R7(#TrpF ,2A}bi@x6t%)@-w Web2 Logic Gate Lab Report As the third lab for course CSIS 110, the logic gate lab allows students to practice their understanding about And, Or, and Not statements. Looking within the library, we do not have this, option. A Truth Table defines how a combination of gates will react to all possible input combinations. A complex electronic system may have many thousands of gates. 0000004295 00000 n
Use of switches as inputs and light emitting diodes (LEDs) or LCD (liquid crystal The truth table ECL is used only in systems requiring high-speed operation. if VDD = 5V, its noise margin is 2V). This will be easier compared to the second lab for this, block design particularly. 
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5 shows a two-input CMOS NAND gate circuit. 0000007220 00000 n
CSIS110 - Logic Gate Lab Report.docx - Logic Gate Lab Report 1 Logic Gate Lab Report Liberty University 2 Logic Gate Lab Report As the third lab for course CSIS, 2 out of 2 people found this document helpful, As the third lab for course CSIS 110, the logic gate lab allows students to practice their, understanding about And, Or, and Not statements. One of them would have the input, connected to X and Y and this output would be connected to the second input XOR gate. Fig. 
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Why are NAND gates and NOR gates sometimes referred to as. 7. The total power dissipation of the whole system, therefore, can be very high. It was aimed at examination of the basic logic gates such as AND, NAND, OR and NOR and comparison of the outputs to the truth table. 
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Figure 1: 1-Bit Adder Schematic Figure 2 below is showing the simulation waveforms for the 1-bit Now. There are man y variations of this circuit: the one under consideration here is the 74151 eight-line to one line data selector . WebLAB REPORT Discussion of Results 1. 0000002673 00000 n
3-2) Draw the reconstructed circuit and logic diagram here (only NAND gates), 3-3) Built the truth table for the reconstructed circuit and measured the voltage for each input/output, Table 5-2 Truth table and volts measured for input/output for the reconstructed circuit. In practice, NAND and NOR gates are economical and easier. At any given moment, every terminal is in one of the two binary 0000005574 00000 n
WebDiscussion: Digital electronics are built using logic gates. endstream
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ciJyYH_PVb53](ZmBFAS~B`k:e5[WUx5e,e(L,GC ,]GW= lx(p% These gates are the basis for building more complex logic circuits that are constructed using various combinations of gates, which is known as Combinational Logic.
However, this is not a required step for this lab. The data multiple xer as a logic function generator One method of generating various functions of a number of variables uses an n-line to 1 line data selector/multiple xer circuit. 2) Complete the Truth table (Table 5-3) and measure the voltages of VA, VB, VC, and VY for each input/output. NOT Gate 6 VII. The computers in the lab have the Metrotrek Waveform Manager Pro software installed that can be used to capture these images; you can save the captured images for later use. endstream
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Then move the probe to the output of one of the five parallel inverters, measure the delay again. WebPart 1. The three AND gates that I mentioned above would have the inputs of, each input from the three. The experiment was also aimed at study of the behavior of the gates such as 74xx series TTL gates by using voltage range of 0 and +5. 0000006036 00000 n
Webc. Most logic gates have two inputs and one output. WebConsider Discussion Topic #4 before continuing. 0000019433 00000 n
Explain your measurements (remember the scope probe is a load; compare its effect with that of 5 parallel loads). 
Draw the circuit for the expression of XNOR Gate using basic gates. 0000005472 00000 n
Draw an input versus output curve with the input ranging from 0V to 5V. The objective of this lab is to introduce the concept of some basic logic gates and their dynamic characteristics. Web- To study the realization of basic gates using universal gates. 0000010276 00000 n
02: For example, if A = 10 and B = 3, This algorithm will perform the following : 10, Run through the following algorithm and determine if 2600 is a leap year YEAR = 2600 Get YEAR STEP 1 If YEAR is equally divisible by 4;Result: True False Not needed This is a Leap This, Run through the following sorting algorithm and determine the largest number. The universality of the NAND and NOR gates means that they can be used as an inverter and the combinations of NAND/NOR gates can be used to implement the AND, OR, and all other logic operations. t(%@ Doing this lab will show us how to develop adder design as well as hierarchical design which. 299 0 obj<>stream
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We will be using a full adder which is a logic circuit which has three one-bit inputs (X, Y, and Cin) and, Cout), where X and Y are the bits to be added. Familiarization with the breadboard 2. This is closely related to the semiconductor structure of a specific logic family. 0000009339 00000 n
f?3-]T2j),l0/%b The power supply for CMOS ICs ranges from 3V to 15V. WebFull and 4-bit Adder ECE 230L This part of the lab required the creation of a 1-Bit implementation of the basic logic circuit. %PDF-1.5
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Digital IC gates are classified not only by their logic operation, but also the specific logic-circuit family to which they belong. This preview shows page 1 - 3 out of 7 pages. 
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The power supply for TTL ICs usually is 5V. It is made up of a p-type MOS transistor and a n-type MOS transistor. 0000008325 00000 n
WebLab Work: (All Lab work must be shown in the Lab report) For the following logic gates, verify the logic operation each gate performs: a. endstream
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